一套用于晶圆上3D-TRL校准的测试结构

2016 International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2016-03-28 DOI:10.1109/ICMTS.2016.7476182

Manuel Potércau, A. Curutchet, R. D’Esposito, M. De matos, S. Frégonèse, T. Zimmer

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引用次数: 3

摘要

本文提出了一种用于晶圆上3D-TRL校准的新型测试结构。它允许在金属1水平上定义后端线以下的参考平面。只需要一个额外的测试结构来考虑输入和输出端口之间的耦合。测量精度已达到1fF以下。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A test structure set for on-wafer 3D-TRL calibration

This paper presents a new test structure set for on-wafer 3D-TRL calibration. It permits to define the reference plane below the Back-End-of-Line on Metal 1 level. Only one additional test structure is necessary to account for the coupling between input and output ports. Measurement accuracy below 1fF has been achieved.

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2016 International Conference on Microelectronic Test Structures (ICMTS)

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