一个800 Mb/s的物理层LSI混合端口架构，用于消费电子网络

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992945

T. Yoshikawk, T. Yoshida, T. Ebuchi, Y. Arima, T. Iwata, K. Nishimura, H. Kimura, Y. Komatsu, H. Yamauchi

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引用次数: 0

摘要

一个物理层LSI有1个DS-port和2个/spl beta/port，分别符合IEEE1394-2000和P1394b Draft 1.01标准。0.25 /spl mu/m的CMOS LSI通过/spl beta/端口实现800mb /s和1.2 km的对等IEEE1394网络。每个/spl beta/端口需要180mw有功功率，并被视为未来大型系统集成的ASIC宏。

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An 800 Mb/s physical layer LSI with hybrid port architecture for consumer electronics networking

A physical layer LSI has one DS-port and two /spl beta/ports in accordance with IEEE1394-2000 and P1394b Draft 1.01 respectively. The 0.25 /spl mu/m CMOS LSI realizes 800 Mb/s and 1.2 km peer-to-peer IEEE1394 networking through /spl beta/port. Each /spl beta/port requires 180 mW active power and is treated as ASIC macro for future large system integration.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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