{"title":"采用多尺度法计算高电感VLSI互连匝道响应的阈值穿越时间","authors":"A. Ligocka, W. Bandurski","doi":"10.1109/SPI.2008.4558391","DOIUrl":null,"url":null,"abstract":"The paper presents a new method of deriving the closed form formula for the output voltage and threshold crossing time for low-loss on-chip upper layer interconnects The threshold crossing time solution for the ramp excitation is derived. The calculation of output voltage of two coupled interconnects for the ramp input is also presented.","PeriodicalId":142239,"journal":{"name":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Using Multiple Scales Method to calculate threshold crossing time for the ramp response for high inductance VLSI interconnects\",\"authors\":\"A. Ligocka, W. Bandurski\",\"doi\":\"10.1109/SPI.2008.4558391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a new method of deriving the closed form formula for the output voltage and threshold crossing time for low-loss on-chip upper layer interconnects The threshold crossing time solution for the ramp excitation is derived. The calculation of output voltage of two coupled interconnects for the ramp input is also presented.\",\"PeriodicalId\":142239,\"journal\":{\"name\":\"2008 12th IEEE Workshop on Signal Propagation on Interconnects\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-05-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 12th IEEE Workshop on Signal Propagation on Interconnects\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPI.2008.4558391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPI.2008.4558391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Using Multiple Scales Method to calculate threshold crossing time for the ramp response for high inductance VLSI interconnects
The paper presents a new method of deriving the closed form formula for the output voltage and threshold crossing time for low-loss on-chip upper layer interconnects The threshold crossing time solution for the ramp excitation is derived. The calculation of output voltage of two coupled interconnects for the ramp input is also presented.