H. Barthélemy, S. Bourdel, N. Dehaese, M. Egels, J. Gaubert, P. Pannier, G. Bas
{"title":"用于802.15.4 SoC的RF CMOS收发器","authors":"H. Barthélemy, S. Bourdel, N. Dehaese, M. Egels, J. Gaubert, P. Pannier, G. Bas","doi":"10.1109/RWS.2006.1615222","DOIUrl":null,"url":null,"abstract":"Feasibility of low cost 2.4 GHz RF CMOS transceiver for the 802.15.4 standard is demonstrated. The system architecture and its constitutive blocs are designed to achieve low cost and low power consumption. The implementation in a 0.28 /spl mu/m standard CMOS process and the packaging methodology to reduce the digital noise is also presented and discussed.","PeriodicalId":244560,"journal":{"name":"2006 IEEE Radio and Wireless Symposium","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"RF CMOS transceiver for 802.15.4 SoC\",\"authors\":\"H. Barthélemy, S. Bourdel, N. Dehaese, M. Egels, J. Gaubert, P. Pannier, G. Bas\",\"doi\":\"10.1109/RWS.2006.1615222\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Feasibility of low cost 2.4 GHz RF CMOS transceiver for the 802.15.4 standard is demonstrated. The system architecture and its constitutive blocs are designed to achieve low cost and low power consumption. The implementation in a 0.28 /spl mu/m standard CMOS process and the packaging methodology to reduce the digital noise is also presented and discussed.\",\"PeriodicalId\":244560,\"journal\":{\"name\":\"2006 IEEE Radio and Wireless Symposium\",\"volume\":\"117 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Radio and Wireless Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS.2006.1615222\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2006.1615222","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Feasibility of low cost 2.4 GHz RF CMOS transceiver for the 802.15.4 standard is demonstrated. The system architecture and its constitutive blocs are designed to achieve low cost and low power consumption. The implementation in a 0.28 /spl mu/m standard CMOS process and the packaging methodology to reduce the digital noise is also presented and discussed.
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