Wei-Chang Liu, Chih-Hsien Lin, S. Jou, Hungwen Lu, Chau-chin Su, Kai-Wei Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, M. Sheu
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A micro-network on chip with 10-Gb/s transmission link
In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm∗1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.
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