使用集成数据分配和实时任务调度的可预测快速内存的技术和工具

Sangyeol Kang, A. Dean
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引用次数: 15

摘要

硬件管理的缓存引入了大量的时间可变性,使实时系统设计复杂化。一种替代方案是带有刮擦板存储器的存储系统,它在消除这种时间可变性的同时提高了系统性能。先前的工作介绍了DARTS方法,该方法将数据静态分配到临时存储器中,并将任务调度用于抢占式多线程、硬实时嵌入式系统。这项研究提供了几个重要的贡献。首先,它引入了一种跨多个内存单元拆分堆栈帧的方法,以非常低的运行时开销为自动内存变量提供细粒度分配。这可以更有效地使用快速内存,改善运行时间。其次,介绍了基于dart的完整工具链,它可以跨多个内存库重新分配静态和自动变量,现在针对ARM7架构。第三,在基于抢占调度rtos的多任务环境中,使用实际硬件上运行的代码的实验结果来评估dart的性能改进。这种动手实验方法确保了对结果的高度信心;以前的研究通常停留在评估性能上,而不是构建和测量实际的实现。在我们的实验中,每个任务的执行时间比基线外部SRAM配置减少了24%。我们表明,我们的方法改进了任务执行时间,达到理想的无限容量刮记板存储系统性能改进的37%到99%。最后,我们发现我们的分配平均提供了同等大小缓存的2/3的性能增强,而且性能很容易预测。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which improve system performance while eliminating such timing variability. Prior work introduced the DARTS approach, which combines static allocation of data into scratchpad memories, with task scheduling for preemptive multi-threaded, hard real-time embedded systems.This study offers several significant contributions. First, it introduces a method to split a stack frame across multiple memory units, offering fine-grain allocation of automatic memory variables with very low run-time overhead. This enables more effective use of fast memory, improving run-times. Second, it introduces the completed tool-chain based on DARTS, which reallocates static and automatic variables across multiple memory banks and now targets the ARM7 architecture. Third, it evaluates the performance improvement from DARTS using experimental results from the code running on real hardware in a preemptively scheduled RTOS-based multi-tasking environment. This hands-on experimental approach ensures a high level of confidence in the results; previous studies have generally stopped at estimating performance rather than building and measuring a real implementation.In our experiments the execution time of each task is reduced up to 24% from the baseline external SRAM configurations. We show that our methods improve task execution time to achieve 37% to 99% of the performance improvement of an ideal unlimited-capacity scratchpad memory system. Finally, we find our allocations provide on average 2/3 of the performance enhancement of the equivalently-sized cache yet with easily-predicted performance.
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