低Vt变异性的体平面SiGe量子阱ZRAM

2015 IEEE International Memory Workshop (IMW) Pub Date : 2015-05-17 DOI:10.1109/IMW.2015.7150268

S. Dutta, S. Mittal, S. Lodha, J. Schulze, U. Ganguly

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引用次数: 2

摘要

与基于SOI或FinFET的设计相比，从简单性、成本和可扩展性的角度来看，平面体ZRAM具有吸引力。另外，高掺杂的p通道体平面ZRAM具有静电电位阱存储，容易受到随机掺杂波动(RDF)引起的VT变化。在这里，我们提出并评估了一种平面体ZRAM器件，该器件具有在n+Si阱上外延生长的Si/SiGe/Si异质结构的固有通道。TCAD仿真结果表明，在+/-1.5V工作状态下，该电路具有660mV的VT位移和45μA/μm的IREAD差。在基于RDF的VT变异性方面，观察到的σVT为12.8 mV，估计是估计VT移位(660mV)的一小部分(~51倍)，与基于p掺杂的通道ZRAM相比低6.47倍。在MOSCAP器件上的初步实验验证了SiGe井中的孔存储，具有0.5V VT位移和良好的读干扰(>1000s)。

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A Bulk Planar SiGe Quantum-Well Based ZRAM with Low Vt Variability

A planar bulk ZRAM is attractive from a simplicity, cost and scalability perspective - compared to SOI or FinFET based designs. Alternatively, the highly doped p-channel bulk planar ZRAM with electrostatic potential well-based hole-storage is susceptible to random- dopant-fluctuation (RDF) induced VT variability. Here, we propose and evaluate a planar bulk ZRAM device with an intrinsic channel of Si/SiGe/Si hetero-structure epitaxially grown on an n+Si well. TCAD simulations show excellent performance of 660mV VT shift at +/-1.5V operation and IREAD difference of 45μA/μm. In terms of RDF based VT variability, a σVT of 12.8 mV is observed which is estimated to be a small fraction (~51×) of the estimate VT shift (660mV) and 6.47× lower compared to p-doped channel based ZRAM. Initial experiments on MOSCAP devices validate the hole-storage in the SiGe well with a 0.5V VT shift and an excellent read disturb (>1000s).

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2015 IEEE International Memory Workshop (IMW)

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