{"title":"一种快速准确的全cmos电路表征方法","authors":"R. Llopis, H. Kerkhoff","doi":"10.1109/EURDAC.1992.246211","DOIUrl":null,"url":null,"abstract":"A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A fast and accurate characterization method for full-CMOS circuits\",\"authors\":\"R. Llopis, H. Kerkhoff\",\"doi\":\"10.1109/EURDAC.1992.246211\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<<ETX>>\",\"PeriodicalId\":218056,\"journal\":{\"name\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1992.246211\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246211","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fast and accurate characterization method for full-CMOS circuits
A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<>
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