{"title":"工作电压低于9V的线性模式CMOS兼容p-n结雪崩光电二极管","authors":"M. M. Hossain, P. Zarkesh-Ha, M. Hayat","doi":"10.1109/IPCON.2015.7323686","DOIUrl":null,"url":null,"abstract":"This paper reports linear-mode p-n junction silicon avalanche photodiodes (APD) fabricated in 1 μm standard CMOS process. Measured mean gain of ~50 was obtained at a sufficiently low operating voltage of 8.7 V.","PeriodicalId":375462,"journal":{"name":"2015 IEEE Photonics Conference (IPC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Linear mode CMOS compatible p-n junction avalanche photodiode with operating voltage below 9V\",\"authors\":\"M. M. Hossain, P. Zarkesh-Ha, M. Hayat\",\"doi\":\"10.1109/IPCON.2015.7323686\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports linear-mode p-n junction silicon avalanche photodiodes (APD) fabricated in 1 μm standard CMOS process. Measured mean gain of ~50 was obtained at a sufficiently low operating voltage of 8.7 V.\",\"PeriodicalId\":375462,\"journal\":{\"name\":\"2015 IEEE Photonics Conference (IPC)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Photonics Conference (IPC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPCON.2015.7323686\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Photonics Conference (IPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPCON.2015.7323686","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Linear mode CMOS compatible p-n junction avalanche photodiode with operating voltage below 9V
This paper reports linear-mode p-n junction silicon avalanche photodiodes (APD) fabricated in 1 μm standard CMOS process. Measured mean gain of ~50 was obtained at a sufficiently low operating voltage of 8.7 V.
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