{"title":"VLSI上实现海马非线性系统模型","authors":"O. Chen, T. Berger, B. Sheu","doi":"10.1109/ICNN.1994.374521","DOIUrl":null,"url":null,"abstract":"The nonlinear model of the functional properties of the hippocampal formation has been developed. The architecture of the proposed hardware implementation has a topology highly similar to the anatomical structure of the hippocampus, and the dynamical properties of its components are based on experimental characterization of individual hippocampal neurons. The design scheme of a analog cellular neural network has been extensively applied. By using a 1-/spl mu/m CMOS technology, the 5/spl times/5 neuron array with some testing modules has been designed for fabrication. According to the SPICE-3 circuit simulator, the response time of each neuron with memorizing 4 time units is around 0.5 /spl mu/sec.<<ETX>>","PeriodicalId":209128,"journal":{"name":"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"VLSI implementation of the hippocampus on nonlinear system model\",\"authors\":\"O. Chen, T. Berger, B. Sheu\",\"doi\":\"10.1109/ICNN.1994.374521\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The nonlinear model of the functional properties of the hippocampal formation has been developed. The architecture of the proposed hardware implementation has a topology highly similar to the anatomical structure of the hippocampus, and the dynamical properties of its components are based on experimental characterization of individual hippocampal neurons. The design scheme of a analog cellular neural network has been extensively applied. By using a 1-/spl mu/m CMOS technology, the 5/spl times/5 neuron array with some testing modules has been designed for fabrication. According to the SPICE-3 circuit simulator, the response time of each neuron with memorizing 4 time units is around 0.5 /spl mu/sec.<<ETX>>\",\"PeriodicalId\":209128,\"journal\":{\"name\":\"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICNN.1994.374521\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICNN.1994.374521","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VLSI implementation of the hippocampus on nonlinear system model
The nonlinear model of the functional properties of the hippocampal formation has been developed. The architecture of the proposed hardware implementation has a topology highly similar to the anatomical structure of the hippocampus, and the dynamical properties of its components are based on experimental characterization of individual hippocampal neurons. The design scheme of a analog cellular neural network has been extensively applied. By using a 1-/spl mu/m CMOS technology, the 5/spl times/5 neuron array with some testing modules has been designed for fabrication. According to the SPICE-3 circuit simulator, the response time of each neuron with memorizing 4 time units is around 0.5 /spl mu/sec.<>
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