一种亚90nm动态电路的工艺变化补偿技术

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221203

Chris H. Kim, Kaushik Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, S. Borkar

{"title":"一种亚90nm动态电路的工艺变化补偿技术","authors":"Chris H. Kim, Kaushik Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2003.1221203","DOIUrl":null,"url":null,"abstract":"A process variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"55","resultStr":"{\"title\":\"A process variation compensating technique for sub-90 nm dynamic circuits\",\"authors\":\"Chris H. Kim, Kaushik Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, S. Borkar\",\"doi\":\"10.1109/VLSIC.2003.1221203\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A process variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.\",\"PeriodicalId\":270304,\"journal\":{\"name\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"55\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2003.1221203\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221203","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 55

摘要

描述了一种用于泄漏变化严重的90纳米以下动态电路的工艺变化补偿技术。在90纳米双v /sub / CMOS中，与传统的静态保持器设计相比，有效强度可基于芯片泄漏优化编程的保持器可使性能提高10%，延迟变化减少35%，鲁棒性失效模具减少5倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A process variation compensating technique for sub-90 nm dynamic circuits

A process variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

自引率

0.00%

发文量