{"title":"低功耗神经模糊脉冲流系统","authors":"M. Chiaberge, E. Miranda Sologuren, L. Reyneri","doi":"10.1109/MNNFS.1996.493791","DOIUrl":null,"url":null,"abstract":"This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A low-power Neuro-Fuzzy pulse stream system\",\"authors\":\"M. Chiaberge, E. Miranda Sologuren, L. Reyneri\",\"doi\":\"10.1109/MNNFS.1996.493791\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit.\",\"PeriodicalId\":151891,\"journal\":{\"name\":\"Proceedings of Fifth International Conference on Microelectronics for Neural Networks\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Fifth International Conference on Microelectronics for Neural Networks\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MNNFS.1996.493791\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNNFS.1996.493791","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit.