基于14nm FinFET的全数字CDR 0.8V电源25Gbps下采样器和鉴相电路

2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE) Pub Date : 2021-12-16 DOI:10.1109/ICSTCEE54422.2021.9708558

Sai Bhargav Sriramoju, Subhakumar Reddy Ankireddypalli

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引用次数: 0

摘要

本文介绍了14nm技术节点(FinFET)下采样器和鉴相器电路的设计。设计是在cadence virtuoso上进行的，电源电压为0.8V，跨工艺角(ss, sf, tt, fs, ff)。所设计的下采样器和鉴相器电路符合全数字时钟和数据恢复(ADCDR)电路，适用于每通道速度为25Gbps的4通道无源光网络，功耗为0.9728 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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14nm FinFET based 0.8V Supply 25Gbps Subsampler and Phase Detector Circuits for All Digital CDR

In this paper, the design of subsampler and phase detector circuits at 14nm technology node (FinFET) is presented. The design is carried out on cadence virtuoso with a supply voltage of 0.8V and across process corners (ss, sf, tt, fs, ff). The designed subsampler and phase detector circuits are in compliance with the All-digital clock and data recovery (ADCDR) circuit and which is applicable to passive optical networks of 4 channels with a speed of 25Gbps per channel by consuming a power dissipation of 0.9728 mW.

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2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE)

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