N. Patkar, A. Katsuno, Simon Li, Tak Maruyama, S. Savkar, M. Simone, G. Shen, R. Swami, D. Tovey
{"title":"HaL处理器的微架构","authors":"N. Patkar, A. Katsuno, Simon Li, Tak Maruyama, S. Savkar, M. Simone, G. Shen, R. Swami, D. Tovey","doi":"10.1109/CMPCON.1995.512394","DOIUrl":null,"url":null,"abstract":"The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"Microarchitecture of HaL's CPU\",\"authors\":\"N. Patkar, A. Katsuno, Simon Li, Tak Maruyama, S. Savkar, M. Simone, G. Shen, R. Swami, D. Tovey\",\"doi\":\"10.1109/CMPCON.1995.512394\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.\",\"PeriodicalId\":415918,\"journal\":{\"name\":\"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway\",\"volume\":\"92 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPCON.1995.512394\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1995.512394","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19
摘要
HaL PM1 CPU是64位SPARC Version 9指令集架构的第一个实现。该处理器利用超标量指令发出、寄存器重命名和执行的数据流模型。指令可以乱序完成，然后按顺序提交。PM1 CPU保持精确状态。该处理器的可靠性比目前商业市场上的台式计算机更高。
The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
