将基于周期的仿真技术应用于VITAL作为VHDL门电平标准

Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555) Pub Date : 2001-05-13 DOI:10.1109/CCECE.2001.933592

B. H. Yaran, Dara Rahmati, A. Zebardast

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引用次数: 1

摘要

仿真引擎是自动化硬件设计过程中的重要组成部分。另一方面，仿真引擎设计的尺寸和复杂性以及速度的限制导致了仿真加速和验证的先进概念。本文介绍了一种基于VITAL周期的仿真器的实现方法，该仿真器利用VITAL标准的潜在能力进行VHDL门电平的快速仿真。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Applying cycle-based simulation technique to VITAL as a VHDL gate level standard

Simulation engines are a major part of automatic hardware design process. On the other hand the size and complexity of designs and limitation of the speed of simulation engines leads to the advanced concepts in simulation acceleration and verification. In this paper we introduce an implementation of VITAL cycle-based simulator that uses potential abilities of VITAL standard for fast VHDL gate level simulation.

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Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)

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