用于监控SoC电源电压的可调低功耗电路

Rodrigo Duarte, J. Paisana, Marcelino B. Santos, Floriberto A. Lima
{"title":"用于监控SoC电源电压的可调低功耗电路","authors":"Rodrigo Duarte, J. Paisana, Marcelino B. Santos, Floriberto A. Lima","doi":"10.1109/APCCAS.2008.4746038","DOIUrl":null,"url":null,"abstract":"This paper proposes an architecture for a power good comparator (PGC) designed to be used in the monitorization of supply voltages of a system-on-chip (SoC). The architecture includes a string of resistors, a comparator, a programmable debouncer and two multiplexers. This architecture was design for very low power consumption and to monitor 4 VDDs. I was implemented using TSMC 65 nm CMOS technology for VDD values of 0.9, 1.2, 1.8 and 3.3 V, with 8 programmable levels of debouncing from 3.2 mus to 32.4 mus. The PGC maximum consumption is 3.54 muA. The output signal presents a digitally adjustable hysteresis curve, with a high threshold voltage of 93% and a low threshold voltage of 90% of VDD. Practical implementation details are presented, namely the requirement for level-converters and for a bulk bias selector in the input multiplexer.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Adjustable low consumption circuit for monitorization of power source voltages in a SoC\",\"authors\":\"Rodrigo Duarte, J. Paisana, Marcelino B. Santos, Floriberto A. Lima\",\"doi\":\"10.1109/APCCAS.2008.4746038\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an architecture for a power good comparator (PGC) designed to be used in the monitorization of supply voltages of a system-on-chip (SoC). The architecture includes a string of resistors, a comparator, a programmable debouncer and two multiplexers. This architecture was design for very low power consumption and to monitor 4 VDDs. I was implemented using TSMC 65 nm CMOS technology for VDD values of 0.9, 1.2, 1.8 and 3.3 V, with 8 programmable levels of debouncing from 3.2 mus to 32.4 mus. The PGC maximum consumption is 3.54 muA. The output signal presents a digitally adjustable hysteresis curve, with a high threshold voltage of 93% and a low threshold voltage of 90% of VDD. Practical implementation details are presented, namely the requirement for level-converters and for a bulk bias selector in the input multiplexer.\",\"PeriodicalId\":344917,\"journal\":{\"name\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2008.4746038\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2008.4746038","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种用于片上系统(SoC)电源电压监测的功率良好比较器(PGC)体系结构。该体系结构包括一串电阻、一个比较器、一个可编程除杂器和两个多路复用器。该体系结构是为非常低的功耗和监控4个vdd而设计的。I采用台积电65nm CMOS技术实现,VDD值为0.9,1.2,1.8和3.3 V,具有8个可编程电平,从3.2 μ s到32.4 μ s。PGC最大功耗为3.54 muA。输出信号呈现数字可调迟滞曲线,高阈值电压为93%,低阈值电压为VDD的90%。给出了具体的实现细节,即对电平转换器和输入多路复用器中批量偏置选择器的要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Adjustable low consumption circuit for monitorization of power source voltages in a SoC
This paper proposes an architecture for a power good comparator (PGC) designed to be used in the monitorization of supply voltages of a system-on-chip (SoC). The architecture includes a string of resistors, a comparator, a programmable debouncer and two multiplexers. This architecture was design for very low power consumption and to monitor 4 VDDs. I was implemented using TSMC 65 nm CMOS technology for VDD values of 0.9, 1.2, 1.8 and 3.3 V, with 8 programmable levels of debouncing from 3.2 mus to 32.4 mus. The PGC maximum consumption is 3.54 muA. The output signal presents a digitally adjustable hysteresis curve, with a high threshold voltage of 93% and a low threshold voltage of 90% of VDD. Practical implementation details are presented, namely the requirement for level-converters and for a bulk bias selector in the input multiplexer.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信