这一切都是关于数据移动:优化FPGA数据访问以提高性能

Nick Brown, D. Dolman
{"title":"这一切都是关于数据移动:优化FPGA数据访问以提高性能","authors":"Nick Brown, D. Dolman","doi":"10.1109/H2RC49586.2019.00006","DOIUrl":null,"url":null,"abstract":"The use of reconfigurable computing, and FPGAs in particular, to accelerate computational kernels has the potential to be of great benefit to scientific codes and the HPC community in general. However, whilst recent advanced in FPGA tooling have made the physical act of programming reconfigurable architectures much more accessible, in order to gain good performance the entire algorithm must be rethought and recast in a dataflow style. Reducing the cost of data movement for all computing devices is critically important, and in this paper we explore the most appropriate techniques for FPGAs. We do this by describing the optimisation of an existing FPGA implementation of an atmospheric model's advection scheme. By taking an FPGA code that was over four times slower than running on the CPU, mainly due to data movement overhead, we describe the profiling and optimisation strategies adopted to significantly reduce the runtime and bring the performance of our FPGA kernels to a much more practical level for real-world use. The result of this work is a set of techniques, steps, and lessons learnt that we have found significantly improves the performance of FPGA based HPC codes and that others can adopt in their own codes to achieve similar results.","PeriodicalId":413478,"journal":{"name":"2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"It's All About Data Movement: Optimising FPGA Data Access to Boost Performance\",\"authors\":\"Nick Brown, D. Dolman\",\"doi\":\"10.1109/H2RC49586.2019.00006\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The use of reconfigurable computing, and FPGAs in particular, to accelerate computational kernels has the potential to be of great benefit to scientific codes and the HPC community in general. However, whilst recent advanced in FPGA tooling have made the physical act of programming reconfigurable architectures much more accessible, in order to gain good performance the entire algorithm must be rethought and recast in a dataflow style. Reducing the cost of data movement for all computing devices is critically important, and in this paper we explore the most appropriate techniques for FPGAs. We do this by describing the optimisation of an existing FPGA implementation of an atmospheric model's advection scheme. By taking an FPGA code that was over four times slower than running on the CPU, mainly due to data movement overhead, we describe the profiling and optimisation strategies adopted to significantly reduce the runtime and bring the performance of our FPGA kernels to a much more practical level for real-world use. The result of this work is a set of techniques, steps, and lessons learnt that we have found significantly improves the performance of FPGA based HPC codes and that others can adopt in their own codes to achieve similar results.\",\"PeriodicalId\":413478,\"journal\":{\"name\":\"2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/H2RC49586.2019.00006\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/H2RC49586.2019.00006","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15

摘要

使用可重构计算,特别是fpga,来加速计算内核有可能给科学代码和高性能计算社区带来巨大的好处。然而,尽管最近FPGA工具的进步使得编程可重构架构的物理行为更容易实现,但为了获得良好的性能,整个算法必须重新考虑并以数据流风格重新构建。降低所有计算设备的数据移动成本至关重要,在本文中,我们探索了最适合fpga的技术。我们通过描述现有的FPGA实现大气模型的平流方案的优化来实现这一点。通过采用比在CPU上运行慢四倍以上的FPGA代码,主要是由于数据移动开销,我们描述了采用的分析和优化策略,以显着减少运行时并将我们的FPGA内核的性能提高到实际使用的更实用的水平。这项工作的结果是一组技术、步骤和经验教训,我们发现这些技术、步骤和经验教训显著提高了基于FPGA的HPC代码的性能,其他人可以在自己的代码中采用这些代码来实现类似的结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
It's All About Data Movement: Optimising FPGA Data Access to Boost Performance
The use of reconfigurable computing, and FPGAs in particular, to accelerate computational kernels has the potential to be of great benefit to scientific codes and the HPC community in general. However, whilst recent advanced in FPGA tooling have made the physical act of programming reconfigurable architectures much more accessible, in order to gain good performance the entire algorithm must be rethought and recast in a dataflow style. Reducing the cost of data movement for all computing devices is critically important, and in this paper we explore the most appropriate techniques for FPGAs. We do this by describing the optimisation of an existing FPGA implementation of an atmospheric model's advection scheme. By taking an FPGA code that was over four times slower than running on the CPU, mainly due to data movement overhead, we describe the profiling and optimisation strategies adopted to significantly reduce the runtime and bring the performance of our FPGA kernels to a much more practical level for real-world use. The result of this work is a set of techniques, steps, and lessons learnt that we have found significantly improves the performance of FPGA based HPC codes and that others can adopt in their own codes to achieve similar results.
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