{"title":"电路对COMFET™(IGT)动态锁存电流的影响","authors":"H. R. Ronan, C. Wheatley","doi":"10.1109/PESC.1986.7415548","DOIUrl":null,"url":null,"abstract":"Terminal measurements are made to verify that latching varies with gate drive resistance and occurs during turn off. dv/dt is varied from 1600 to 300 V/us with no impact on latch. A time-displaced turn-off current pulse demonstrates that latching occurs at very low drain voltages, suggesting a tailored gate drive. A brief discussion of device structure explains the observations.","PeriodicalId":164857,"journal":{"name":"1986 17th Annual IEEE Power Electronics Specialists Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1986-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Circuit influences on COMFET™ (IGT) dynamic latching current\",\"authors\":\"H. R. Ronan, C. Wheatley\",\"doi\":\"10.1109/PESC.1986.7415548\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Terminal measurements are made to verify that latching varies with gate drive resistance and occurs during turn off. dv/dt is varied from 1600 to 300 V/us with no impact on latch. A time-displaced turn-off current pulse demonstrates that latching occurs at very low drain voltages, suggesting a tailored gate drive. A brief discussion of device structure explains the observations.\",\"PeriodicalId\":164857,\"journal\":{\"name\":\"1986 17th Annual IEEE Power Electronics Specialists Conference\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1986-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 17th Annual IEEE Power Electronics Specialists Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PESC.1986.7415548\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 17th Annual IEEE Power Electronics Specialists Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PESC.1986.7415548","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Circuit influences on COMFET™ (IGT) dynamic latching current
Terminal measurements are made to verify that latching varies with gate drive resistance and occurs during turn off. dv/dt is varied from 1600 to 300 V/us with no impact on latch. A time-displaced turn-off current pulse demonstrates that latching occurs at very low drain voltages, suggesting a tailored gate drive. A brief discussion of device structure explains the observations.