Software-Specified FPGA Accelerators for Elementary Functions

We use a high-level synthesis (HLS) methodology for the design of hardware accelerators for two elementary functions: reciprocal and square root. The functions are described in C-language software and synthesized into Verilog RTL using the LegUp HLS tool from the University of Toronto [1]. The accelerators are designed to deliver high accuracy, and provide less than 1 ULP error in comparison with GNU software (math.h). Through changes to the HLS constraints, hardware implementations with different speed/area trade-offs can be generated rapidly. In an experimental study, our HLS-generated accelerators are targeted to the Altera/Intel Cyclone V FPGA and compared with hand-designed cores from the FPGA vendor. Results show that our cores offer considerably better resource usage (area) (i.e. ALMs, DSPs, memory bits), while commercial cores operate at a modestly higher FMax.