A systolic algorithm and architecture for Galois field arithmetic

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. The paper presents a new algorithm for computing multiplication and division in GF(2/sup m/). A systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle. The architecture can be realized as a VLSI chip that can yield a computational rate of 40 million multiplications/divisions per second.<>