RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory

A pipeline of processors can increase the throughput of streaming applications significantly. Communication between processors in such a system can occur via FIFOs, shared memory or both. The use of a cache for the shared memory can improve performance. To see the effect of differing cache configurations (size, line size and associativity) on performance, typical full system simulations for each differing cache configuration must be performed. Rapid estimation of performance is difficult due to the cache being accessed by many processors. In this paper, for the first time, we show a method to estimate the performance of a pipelined processor system in the presence of differing sizes of caches which connect to the main memory. By performing just a few full simulations for a few cache configurations, and by using these simulations to estimate the hits and misses for other configurations, and then by carefully annotating the times of traces by the estimated hits and misses, we are able to estimate the throughput of a pipelined system to within 90% of its actual value. The estimation time takes less than 10% of full simulation time. The estimated values have a fidelity of 0.97 on average (1 being perfectly correlated) with the actual values.