具有全摆压节点的14晶体管CMOS全加法器

M. Vesterbacka
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引用次数: 161

摘要

我们解释了如何使用异或或非电路(XOR/XNOR)来实现基于通路晶体管的通用全加法器电路。在通用全加法器中引入了一个六晶体管CMOS异或电路,该电路也能产生互补的异或输出。所得到的全加法器电路仅使用14个mosfet实现,同时在所有电路节点中具有全电压摆幅。对于所提出的全加法器电路和另一个基于通路晶体管的16晶体管全加法器电路,已经以0.35 /spl mu/m的工艺进行了布局。通过对比HSPICE对两种布局的仿真结果,对所提全加法器的性能进行了评价。这两种加法器在功耗、功率延迟积和传播延迟方面产生相似的性能。由于减少了器件计数,所建议的加法器的面积略低。然而,由于所建议的加法器中需要对两个反馈mosfet进行比率处理,因此所建议的加法器的设计成本较高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 14-transistor CMOS full adder with full voltage-swing nodes
We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also produces a complementary XNOR output is introduced in the general full adder. The resulting full adder circuit is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes. Layouts have been made in a 0.35 /spl mu/m process for both the proposed full adder circuit and another 16-transistor full adder circuit based on pass transistors. The performance of the proposed full adder is evaluated by comparison of the simulation results obtained from HSPICE for both layouts. The two adders yield similar performance in terms of power consumption, power delay product, and propagation delay. The area is somewhat lower for the proposed adder due to the reduced device count. However, due to two feedback MOSFETs in the proposed adder that need to be ratioed, there is a higher cost in terms of design effort for the proposed adder.
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