{"title":"带分隔符匹配应用的编译器堆栈的片上系统实现","authors":"Sarmad F. Ismael, Omar T. Zyad, Y. Qassim","doi":"10.1109/SCEE.2018.8684137","DOIUrl":null,"url":null,"abstract":"In this paper, multiple stacks are implemented in software and multi-core hardware System on Chip for suitability and improvement of performance speed. The hardware stacks are tested with the application of delimiter matching in a program and they showed faster run time compared to the software-based stacks. The implemented design of 16 programmable logic cores on the Xilinx Zynq-7000 chip located on the Zybo board has achieved a run time of 13.9ms when applying a matching delimiter test on a code of 16 random equations written in C language.","PeriodicalId":357053,"journal":{"name":"2018 Third Scientific Conference of Electrical Engineering (SCEE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"System on Chip Implementation of Compiler Stack with a Delimiter Matching Application\",\"authors\":\"Sarmad F. Ismael, Omar T. Zyad, Y. Qassim\",\"doi\":\"10.1109/SCEE.2018.8684137\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, multiple stacks are implemented in software and multi-core hardware System on Chip for suitability and improvement of performance speed. The hardware stacks are tested with the application of delimiter matching in a program and they showed faster run time compared to the software-based stacks. The implemented design of 16 programmable logic cores on the Xilinx Zynq-7000 chip located on the Zybo board has achieved a run time of 13.9ms when applying a matching delimiter test on a code of 16 random equations written in C language.\",\"PeriodicalId\":357053,\"journal\":{\"name\":\"2018 Third Scientific Conference of Electrical Engineering (SCEE)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 Third Scientific Conference of Electrical Engineering (SCEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCEE.2018.8684137\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Third Scientific Conference of Electrical Engineering (SCEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCEE.2018.8684137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
System on Chip Implementation of Compiler Stack with a Delimiter Matching Application
In this paper, multiple stacks are implemented in software and multi-core hardware System on Chip for suitability and improvement of performance speed. The hardware stacks are tested with the application of delimiter matching in a program and they showed faster run time compared to the software-based stacks. The implemented design of 16 programmable logic cores on the Xilinx Zynq-7000 chip located on the Zybo board has achieved a run time of 13.9ms when applying a matching delimiter test on a code of 16 random equations written in C language.
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