FPGA power estimation simulator for dynamic input data

As the availability of field-programmable gate arrays (FPGAs) increases, the importance of their power management has become crucial. For an efficient power management scheme, an accurate power estimation is required. The power consumption of FPGAs differs depending on the input, and previous power estimation methods have limitations which make it difficult to predict the input patterns which affect the power consumption of FPGA. Therefore, we propose a simulator which is able to estimate the power in consideration of input data. It estimates the power consumption more accurately at a minute level. From the result of experiment, we identify that there is a great gap on power estimation between previous methods and the proposed one.