{"title":"用于低延迟的ATM网络接口架构","authors":"Patrik Sundström, Per Andersson","doi":"10.1109/ICCCN.1997.623357","DOIUrl":null,"url":null,"abstract":"There are many important factors to consider when designing a network interface for an ATM network, and different applications have different demands. This paper addresses the problem of making an ATM interface with the focus on very low message latency, e.g., for shared memory multiprocessors on top of a network of workstations, and yet making it general enough to be a cost effective solution. Different approaches to the interface are evaluated and an architecture where critical functions are distributed and performed in dedicated hardware, integrated with, or very close to, the processors, are proposed.","PeriodicalId":305733,"journal":{"name":"Proceedings of Sixth International Conference on Computer Communications and Networks","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"ATM network interface architectures for low latency\",\"authors\":\"Patrik Sundström, Per Andersson\",\"doi\":\"10.1109/ICCCN.1997.623357\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"There are many important factors to consider when designing a network interface for an ATM network, and different applications have different demands. This paper addresses the problem of making an ATM interface with the focus on very low message latency, e.g., for shared memory multiprocessors on top of a network of workstations, and yet making it general enough to be a cost effective solution. Different approaches to the interface are evaluated and an architecture where critical functions are distributed and performed in dedicated hardware, integrated with, or very close to, the processors, are proposed.\",\"PeriodicalId\":305733,\"journal\":{\"name\":\"Proceedings of Sixth International Conference on Computer Communications and Networks\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Sixth International Conference on Computer Communications and Networks\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCCN.1997.623357\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Sixth International Conference on Computer Communications and Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCCN.1997.623357","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
ATM network interface architectures for low latency
There are many important factors to consider when designing a network interface for an ATM network, and different applications have different demands. This paper addresses the problem of making an ATM interface with the focus on very low message latency, e.g., for shared memory multiprocessors on top of a network of workstations, and yet making it general enough to be a cost effective solution. Different approaches to the interface are evaluated and an architecture where critical functions are distributed and performed in dedicated hardware, integrated with, or very close to, the processors, are proposed.