A. Phanse, R. Shirani, R. Rasmussen, R. Mendel, J. Yuan
{"title":"锁相外观的行为建模","authors":"A. Phanse, R. Shirani, R. Rasmussen, R. Mendel, J. Yuan","doi":"10.1109/SOUTHC.1996.535101","DOIUrl":null,"url":null,"abstract":"In this paper a methodology for modeling a Phase-Locked-Loop (PLL) has been presented. A behavioral model for the PLL was developed using an Analog Hardware Description Language (AHDL). This behavioral model is accurate with respect to SPICE simulations and provides a speed-up of 1600X over SPICE. The behavioral model was used to simulate the jitter in the generated clock during phase lock and evaluate the effect of the mismatches in the circuit on the jitter.","PeriodicalId":199600,"journal":{"name":"Southcon/96 Conference Record","volume":"102 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Behavioral modeling of a phase locked look\",\"authors\":\"A. Phanse, R. Shirani, R. Rasmussen, R. Mendel, J. Yuan\",\"doi\":\"10.1109/SOUTHC.1996.535101\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a methodology for modeling a Phase-Locked-Loop (PLL) has been presented. A behavioral model for the PLL was developed using an Analog Hardware Description Language (AHDL). This behavioral model is accurate with respect to SPICE simulations and provides a speed-up of 1600X over SPICE. The behavioral model was used to simulate the jitter in the generated clock during phase lock and evaluate the effect of the mismatches in the circuit on the jitter.\",\"PeriodicalId\":199600,\"journal\":{\"name\":\"Southcon/96 Conference Record\",\"volume\":\"102 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-06-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Southcon/96 Conference Record\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOUTHC.1996.535101\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Southcon/96 Conference Record","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOUTHC.1996.535101","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper a methodology for modeling a Phase-Locked-Loop (PLL) has been presented. A behavioral model for the PLL was developed using an Analog Hardware Description Language (AHDL). This behavioral model is accurate with respect to SPICE simulations and provides a speed-up of 1600X over SPICE. The behavioral model was used to simulate the jitter in the generated clock during phase lock and evaluate the effect of the mismatches in the circuit on the jitter.
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