{"title":"一种由无结n-FinFET组成的新型CMOS结构,具有相同的n-通道和公共栅极","authors":"Xinlong Shi, Huiyong Hu, Ying Wang, Liming Wang, Bin Wang, Ningning Zhang","doi":"10.1109/CONIT55038.2022.9847724","DOIUrl":null,"url":null,"abstract":"In this paper, a novel CMOS inverter with the same n-channel and same gate work function has been proposed. This new structure is composed of junctionless (JL) n-FinFET and inversion-mode (IM) p-FinFET. Compared with the conventional CMOS inverter, the novel CMOS device can be fabricated on the same SOI substrates with the same gate material, which simplifies the fabrication process and reduces fabrication costs. The logic performance of CMOS inverters is evaluated using 3D numerical simulation at sub-5 nm technology nodes.The ION/ IOFF ratio of the JL n-FinFET improved up to 3.8%, the intrinsic gain improved up to 4.8% as compared to the IM n-FinFET. The rise time, fall time and RO frequency of the novel CMOS inverter are improved up to 1.8%, 8.5% and 7.6% respectively, compared with the traditional CMOS inverter.","PeriodicalId":270445,"journal":{"name":"2022 2nd International Conference on Intelligent Technologies (CONIT)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Novel CMOS Structure Composed of Junctionless n-FinFET with the Same n-Channel and Common Gate\",\"authors\":\"Xinlong Shi, Huiyong Hu, Ying Wang, Liming Wang, Bin Wang, Ningning Zhang\",\"doi\":\"10.1109/CONIT55038.2022.9847724\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a novel CMOS inverter with the same n-channel and same gate work function has been proposed. This new structure is composed of junctionless (JL) n-FinFET and inversion-mode (IM) p-FinFET. Compared with the conventional CMOS inverter, the novel CMOS device can be fabricated on the same SOI substrates with the same gate material, which simplifies the fabrication process and reduces fabrication costs. The logic performance of CMOS inverters is evaluated using 3D numerical simulation at sub-5 nm technology nodes.The ION/ IOFF ratio of the JL n-FinFET improved up to 3.8%, the intrinsic gain improved up to 4.8% as compared to the IM n-FinFET. The rise time, fall time and RO frequency of the novel CMOS inverter are improved up to 1.8%, 8.5% and 7.6% respectively, compared with the traditional CMOS inverter.\",\"PeriodicalId\":270445,\"journal\":{\"name\":\"2022 2nd International Conference on Intelligent Technologies (CONIT)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 2nd International Conference on Intelligent Technologies (CONIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CONIT55038.2022.9847724\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 2nd International Conference on Intelligent Technologies (CONIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONIT55038.2022.9847724","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel CMOS Structure Composed of Junctionless n-FinFET with the Same n-Channel and Common Gate
In this paper, a novel CMOS inverter with the same n-channel and same gate work function has been proposed. This new structure is composed of junctionless (JL) n-FinFET and inversion-mode (IM) p-FinFET. Compared with the conventional CMOS inverter, the novel CMOS device can be fabricated on the same SOI substrates with the same gate material, which simplifies the fabrication process and reduces fabrication costs. The logic performance of CMOS inverters is evaluated using 3D numerical simulation at sub-5 nm technology nodes.The ION/ IOFF ratio of the JL n-FinFET improved up to 3.8%, the intrinsic gain improved up to 4.8% as compared to the IM n-FinFET. The rise time, fall time and RO frequency of the novel CMOS inverter are improved up to 1.8%, 8.5% and 7.6% respectively, compared with the traditional CMOS inverter.