{"title":"Savage16 - 16位RISC架构通用微处理器","authors":"A. Gheorghe, C. Burileanu","doi":"10.1109/SMICND.2010.5650480","DOIUrl":null,"url":null,"abstract":"This paper describes the architecture and the internal structure of “Savage16”, a fully functional general purpose reduced instruction set microprocessor, with a modified Harvard, five stage pipeline architecture. The memory organization and key architecture elements are being described, as well as the hardware block diagram and the internal structure. A summary of the instruction set is presented, along with a brief description of the addressing modes.","PeriodicalId":377326,"journal":{"name":"CAS 2010 Proceedings (International Semiconductor Conference)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Savage16 - 16-bit RISC architecture general purpose microprocessor\",\"authors\":\"A. Gheorghe, C. Burileanu\",\"doi\":\"10.1109/SMICND.2010.5650480\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the architecture and the internal structure of “Savage16”, a fully functional general purpose reduced instruction set microprocessor, with a modified Harvard, five stage pipeline architecture. The memory organization and key architecture elements are being described, as well as the hardware block diagram and the internal structure. A summary of the instruction set is presented, along with a brief description of the addressing modes.\",\"PeriodicalId\":377326,\"journal\":{\"name\":\"CAS 2010 Proceedings (International Semiconductor Conference)\",\"volume\":\"248 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"CAS 2010 Proceedings (International Semiconductor Conference)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.2010.5650480\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"CAS 2010 Proceedings (International Semiconductor Conference)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.2010.5650480","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Savage16 - 16-bit RISC architecture general purpose microprocessor
This paper describes the architecture and the internal structure of “Savage16”, a fully functional general purpose reduced instruction set microprocessor, with a modified Harvard, five stage pipeline architecture. The memory organization and key architecture elements are being described, as well as the hardware block diagram and the internal structure. A summary of the instruction set is presented, along with a brief description of the addressing modes.
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