时序驱动的多fpga板分区

Proceedings Eleventh International Conference on VLSI Design Pub Date : 1998-01-04 DOI:10.1109/ICVD.1998.646609

R. Burra, D. Bhatia

{"title":"时序驱动的多fpga板分区","authors":"R. Burra, D. Bhatia","doi":"10.1109/ICVD.1998.646609","DOIUrl":null,"url":null,"abstract":"System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Timing driven multi-FPGA board partitioning\",\"authors\":\"R. Burra, D. Bhatia\",\"doi\":\"10.1109/ICVD.1998.646609\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.\",\"PeriodicalId\":139023,\"journal\":{\"name\":\"Proceedings Eleventh International Conference on VLSI Design\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Eleventh International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1998.646609\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1998.646609","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

系统级设计越来越多地转向fpga，以利用其低成本和快速原型的优势。在本文中，我们提出了一种时序驱动的分区方法，用于架构受限的多fpga系统。分区方法使用基于Dennis等人(1995)的工作和重新计时的基于路径的聚类。板级架构基于由四个Xilinx 4013 fpga组成的PCB模型。该算法已在大型实际设计中进行了测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Timing driven multi-FPGA board partitioning

System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings Eleventh International Conference on VLSI Design

自引率

0.00%

发文量