Design and Analysis of an Experimental Data and Clock Multiplexing Technique for Generating Faster Single Wire Synchronous Data Bus

This paper describes an experimental multiplexing technique to combine data and clock signal, intended to be used with single wire Bus. The experimental multiplexing technique uses the metastable state of 5v TTL standard to carry clock signal such that a single wire can be used to carry data in synchronous manner without any software based encoding. Computer based simulator is first used to verify the idea and later hardware prototype is constructed to verify the validity of the idea in real world condition. The circuits worked as predicted in the simulator and worked almost perfectly with minor unforeseen glitch in the hardware prototype. The data bit rate of the experimental method is compared to multiple existing one wire data Bus to reveal that the experimental method enables the Bus to carry data at bit rate which is 30% to 62 % higher than the standard bit rate of existing single wire data Bus.