考虑应力频率依赖性的nbti延迟退化研究

Zuitoku Shin, Shumpei Morita, S. Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
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引用次数: 3

摘要

除了众所周知的应力占空比外,集成电路中晶体管的退化还取决于应力频率。本文通过使用不同级别的可用信息,分析了不同工作负载场景下NBTI退化的频率依赖性对处理器级电路的影响。本文还提出了一种从占空比估计导线开关频率的简单方法。通过在MIPS处理器上运行的实际工作负载,发现由于存在许多与频率无关的直流应力分量,因此最坏路径延迟的频率依赖性不大。然而,由于多个应用程序的执行,当直流分量减少时,路径延迟的频率依赖性增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A study on NBTI-induced delay degradation considering stress frequency dependence
The degradation of transistors in integrated circuits is known to be dependent on stress frequency in addition to the well-known stress duty cycle. This paper analyzes the impact of frequency dependence of the NBTI degradation on a processor-scale circuit under various workload scenarios by using different levels of available information. A simple estimation for wire switching frequency from duty cycle is also proposed. Using real workloads running on MIPS processor, it is found that frequency dependency of the worst path delay is not large since there are many DC stress components independent of frequency. However, frequency dependency of path delay increases when DC component decreases due to execution of multiple applications.
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