基于间隔偏移的PUF熵增强算法中可靠对的扩大

Md. Omar Faruque, Wenjie Che
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引用次数: 0

摘要

物理不可克隆函数(puf)是新兴的硬件安全原语,它利用芯片制造过程中的随机变化来生成独特的秘密。可以从有限数量的物理PUF组件中提取的随机秘密的数量可以通过熵位来测量。现有的N个RO-PUF元素配对或分组策略的熵上界限制为log2(N!)或O(N•log2(N))。最近提出的一种熵增强技术[9]将熵位提高到N(N-1)/2或O(N^2)的二次大,显著提高了RO-PUF在生成秘密时的硬件利用率。然而,随机秘密数量的增加是以丢弃大量不可靠比特为代价的。在本文中,我们提出了一种“距离间偏移(IDO)”技术,通过调整对间距离到适当的范围,将那些不可靠的对转换为可靠的对。对转换不可靠位的比率进行了理论分析,并进行了实验验证。在[10]中使用真实RO PUF数据集给出了可靠性、熵和可靠性权衡的实验评估。使用PUF数据集对信息泄漏进行分析和评估,以确定未泄漏信息的偏移范围。在不同的偏移量范围内,该技术将可靠(二次大)熵比特的比例分别提高了20%和100%。在fpga上的硬件实现表明,该技术在实现和运行时都是轻量级的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Enlarging Reliable Pairs via Inter-Distance Offset for a PUF Entropy-Boosting Algorithm
Physically Unclonable Functions (PUFs) are emerging hardware security primitives that leverage random variations during chip fabrication to generate unique secrets. The amount of random secrets that can be extracted from a limited number of physical PUF components can be measured by entropy bits. Existing strategies of pairing or grouping N RO-PUF elements have an entropy upper bound limited by log2(N!) or O(N•log2(N)). A recently proposed entropy boosting technique [9] improves the entropy bits to be quadratically large at N(N-1)/2 or O(N^2), significantly improved the RO-PUF hardware utilization efficiency in generating secrets. However, the improved amount of random secrets comes at the cost of discarding a large portion of unreliable bits. In this paper, we propose an "Inter-Distance Offset (IDO)" technique that converts those unreliable pairs to be reliable by adjusting the pair inter-distance to an appropriate range. Theoretical analysis of the ratio of converted unreliable bits is provided along with experimental validations. Experimental evaluations on reliability, Entropy and reliability tradeoffs are given using real RO PUF datasets in [10]. Information leakage is analyzed and evaluated using PUF datasets to identify those offset ranges that leak no information. The proposed technique improves the portion of reliable (quadratically large) entropy bits by 20% and 100% respectively for different offset ranges. Hardware implementation on FPGAs demonstrates that the proposed technique is lightweight in implementation and runtime.
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