一种低待机功率读无干扰9T SRAM电池

R. M. Kumar, Dr. P. V. Sridevi
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引用次数: 2

摘要

6T SRAM单元的稳定性对低技术节点的待机功率和稳定性提出了主要的设计挑战。随着技术的缩小,待机功耗增加。此外,由于读取电流流经内部存储节点,因此更有可能在内部存储节点上翻转数据,这严重影响了SRAM单元的稳定性。因此,设计了一种新的9T SRAM单元,减少了待机功耗,并与内部存储节点解耦了读取路径,从而解决了上述问题。电路采用45纳米CMOS技术,在0.9V电源电压下使用Cadence Virtuoso进行设计和仿真。与传统的6T SRAM电池相比,P9T电池在工艺角TT、SS、FS和SF上的待机功率分别降低了10.235%、8.8511%、7.2976%和6.5871%。此外,稳定性分析使用蝴蝶曲线在所有过程的角落。在TT、FF、SS、FS和SF下,P9T SRAM单元的读静态噪声裕度分别比6T SRAM单元高103.37%、104.39%、100.54%、136.81%和79.95%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Proposed Low Standby Power Read Disturb-Free 9T SRAM Cell
6T SRAM Cell stability poses a major design challenge at lower technology nodes related to the standby power and also the stability. As the technology shrinks the standby power consumption increases. Also as the read current flows through the internal storage nodes, there is more chance of flipping the data at the internal storage nodes which affects the stability of SRAM cell severely. So a new 9T SRAM cell is designed with reduced standby power and decoupled read path from the internal storage nodes that eliminates the above problem. The Circuits are designed and simulated in 45nm CMOS technology using Cadence Virtuoso at 0.9V supply voltage. There is a reduction of 10.235%, 8.8511%, 7.2976%, 6.5871% standby power for the Proposed Read Disturb Free 9T SRAM(P9T) cell compared to the Conventional 6T SRAM Cell across the process corners TT, SS, FS and SF respectively. Also the stability analysis is done using the Butterfly curve across all process corners. There is a increase of 103.37%, 104.39%, 100.54%, 136.81%, 79.95% Read Static Noise margin in P9T SRAM Cell than the 6T SRAM cell at TT, FF, SS, FS and SF respectively.
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