On the latency bound of deficit round robin

The emerging high-speed broadband packet-switched networks are expected to simultaneously support a variety of services with different quality-of-service (QoS) requirements over the same physical infrastructure. Fair packet scheduling algorithms used in switches and routers play a critical role in providing these QoS guarantees. Deficit round robin (DRR), a popular fair scheduling discipline, is very efficient with an O(l) dequeuing complexity. Using the concept of latency-rate (/spl Lscr//spl Rscr/) servers introduced by Stiliadis and Varma (1996), we obtain an upper bound on the latency of DRR and prove that our bound is tight. Our upper bound is lower than the previously known upper bound. This illustrates that the DRR scheduler has better performance characteristics than previously believed, especially for real-time applications where the latency plays a role in the size of the playback buffer required.