FPGA based Speech Separation using IPD Features

The problem of speaker separation is an established field in science and goes back to the cocktail party problem defined in 1953. For decades, methods have been improved and developed, but the computational complexity is rarely considered just as the possibility to use hardware acceleration mechanisms. For this reason, this paper addresses the research question: how speaker separation can be realized on embedded systems by exploiting parallelization and intelligent hardware/software partitioning. For this purpose, a concept is described which uses an FPGA for parallelization to separate a speech signal from an intended direction providing a constant throughput rate. The implementation results show the independence of FPGA resources except BRAM size, proving the scalability of the concept, just as the real-time capabilities.