对并联开关级故障进行仿真

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI:10.1109/VTEST.1993.313375

C. A. Ryan, J. Tront

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引用次数: 9

摘要

提出了一种新的开关级并行故障仿真扩展方法和并行处理所需的开关级电路划分方法。使用9值逻辑，反向电平排序和并行硬件加速故障模拟器，仿真复杂性降低到O(L**2)，其中L为从输出到输入遍历时遇到的开关电平数

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On parallel switch level fault simulation

Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<>

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Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

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