{"title":"生物医学应用中SAR ADC的轨对轨比较器","authors":"N. ALjehani, M. Abbas","doi":"10.23919/MIXDES52406.2021.9497556","DOIUrl":null,"url":null,"abstract":"this paper presents low voltage low power a rail to rail common mode range clocked comparator. The target application of the proposed circuit is analog to digital converter for biomedical applications. The proposed comparator is composed of two stages which are pre-amplifiers and modified strong-Arm latch. The outputs of NMOS-input and PMOS-input pre-amplifiers are combined by the modified Strong-Arm latch producing rail to rail common mode range clocked comparator. Adopting TSMC 0.18μm technology, the preamplifier stages were designed to work in weak inversion using gm/ID design methodology. The simulation results show that the preamplifier stage consumes less than 0.275μW using power supply of 0.75V. The pre-amplifier DC gain of 43.15dB and unity gain frequency of 300 kHz","PeriodicalId":375541,"journal":{"name":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Rail to Rail Comparator for SAR ADC in Biomedical Applications\",\"authors\":\"N. ALjehani, M. Abbas\",\"doi\":\"10.23919/MIXDES52406.2021.9497556\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"this paper presents low voltage low power a rail to rail common mode range clocked comparator. The target application of the proposed circuit is analog to digital converter for biomedical applications. The proposed comparator is composed of two stages which are pre-amplifiers and modified strong-Arm latch. The outputs of NMOS-input and PMOS-input pre-amplifiers are combined by the modified Strong-Arm latch producing rail to rail common mode range clocked comparator. Adopting TSMC 0.18μm technology, the preamplifier stages were designed to work in weak inversion using gm/ID design methodology. The simulation results show that the preamplifier stage consumes less than 0.275μW using power supply of 0.75V. The pre-amplifier DC gain of 43.15dB and unity gain frequency of 300 kHz\",\"PeriodicalId\":375541,\"journal\":{\"name\":\"2021 28th International Conference on Mixed Design of Integrated Circuits and System\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 28th International Conference on Mixed Design of Integrated Circuits and System\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/MIXDES52406.2021.9497556\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 28th International Conference on Mixed Design of Integrated Circuits and System","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/MIXDES52406.2021.9497556","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Rail to Rail Comparator for SAR ADC in Biomedical Applications
this paper presents low voltage low power a rail to rail common mode range clocked comparator. The target application of the proposed circuit is analog to digital converter for biomedical applications. The proposed comparator is composed of two stages which are pre-amplifiers and modified strong-Arm latch. The outputs of NMOS-input and PMOS-input pre-amplifiers are combined by the modified Strong-Arm latch producing rail to rail common mode range clocked comparator. Adopting TSMC 0.18μm technology, the preamplifier stages were designed to work in weak inversion using gm/ID design methodology. The simulation results show that the preamplifier stage consumes less than 0.275μW using power supply of 0.75V. The pre-amplifier DC gain of 43.15dB and unity gain frequency of 300 kHz