{"title":"CMOS 0.25µm技术室温下总电离剂量硬度增强","authors":"G. Cussac, L. Artola, T. Nuns, S. Ducret","doi":"10.1109/RADECS50773.2020.9857680","DOIUrl":null,"url":null,"abstract":"This work presents electricals characteristics of primary and secondly irradiated MOSFET transistors. Secondly irradiated transistors after nominal operation recovery showed a great TID resistance betterment. This improvement is allowed by latent interface traps charge build-up during long time annealing. Latent interface traps effects on electrical degradation at STI level are physically explained with simulation and experiment comparison.","PeriodicalId":371838,"journal":{"name":"2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Total Ionizing Dose Hardness Enhancement at Room Temperature in CMOS 0.25µm Technology\",\"authors\":\"G. Cussac, L. Artola, T. Nuns, S. Ducret\",\"doi\":\"10.1109/RADECS50773.2020.9857680\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents electricals characteristics of primary and secondly irradiated MOSFET transistors. Secondly irradiated transistors after nominal operation recovery showed a great TID resistance betterment. This improvement is allowed by latent interface traps charge build-up during long time annealing. Latent interface traps effects on electrical degradation at STI level are physically explained with simulation and experiment comparison.\",\"PeriodicalId\":371838,\"journal\":{\"name\":\"2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RADECS50773.2020.9857680\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADECS50773.2020.9857680","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Total Ionizing Dose Hardness Enhancement at Room Temperature in CMOS 0.25µm Technology
This work presents electricals characteristics of primary and secondly irradiated MOSFET transistors. Secondly irradiated transistors after nominal operation recovery showed a great TID resistance betterment. This improvement is allowed by latent interface traps charge build-up during long time annealing. Latent interface traps effects on electrical degradation at STI level are physically explained with simulation and experiment comparison.