10-bit High-speed CMOS comparator with offset cancellation technique

Nowadays, in all modern electronic devices a low voltage with high speed comparator plays an important role in overall performance of the systems. This paper describes the implementation of a high-speed comparator with high-resolution, 10-bit, in 0.18pM CMOS technology drawn from a 1.8 V supply which is suitable for analog-to-digital converter (ADC) applications and for electronic industry. An offset cancellation technique is done and tested in order to decrease the offset and kickback noise. Regarding the Monte Carlo and corner simulation results for 100 samples and 9 corners respectively, it can be observed that bit error rate is approximately zero and comparator can response fast to the input signals. After accessing acceptable simulation results from designed comparator, the layout of each comparator components such as Op-amps, switches, and latch have been drawn and tested in Cadence Spectre Circuit Simulator.