V. Kavinilavu, S. Salivahanan, V. S. K. Bhaaskaran, S. Sakthikumaran, B. Brindha, C. Vinoth
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引用次数: 34
摘要
Viterbi解码器使用Viterbi算法对使用基于卷积码的前向纠错编码的位流进行解码。利用维特比算法实现了数字流的最大似然检测。本文提出了一种约束长度为7、码率为1/2的卷积编码器和Viterbi解码器。这是用Verilog HDL实现的。采用Modelsim PE 10.0e和Xilinx 12.4i进行仿真合成。
Implementation of Convolutional encoder and Viterbi decoder using Verilog HDL
A Viterbi decoder uses the Viterbi algorithm for decoding a bit stream that has been encoded using Forward error correction based on a Convolutional code. The maximum likelihood detection of a digital stream is possible by Viterbi algorithm. In this paper, we present a Convolutional encoder and Viterbi decoder with a constraint length of 7 and code rate of 1/2. This is realized using Verilog HDL. It is simulated and synthesized using Modelsim PE 10.0e and Xilinx 12.4i.
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