嵌入式flash测试:概述和透视图

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Pub Date : 2006-10-16 DOI:10.1109/DTIS.2006.1708721

O. Ginez, J. Daga, P. Girard, C. Landrault, Serge, Pravossoudovitch, A. Virazel

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引用次数: 6

摘要

片上系统(SoC)设计的演变涉及非易失性存储技术的发展，如闪存。嵌入式闪存(eFlash)存储器基于浮栅晶体管的概念，并且可能受到复杂的硬缺陷造成的功能故障的影响。在本文中，我们对一种特殊的破坏机制，即扰动现象进行了完整的分析。此外，我们还分析了特定测试序列检测这种干扰现象的效率。最后，我们总结了开发适合eFlash环境的新测试基础设施的兴趣

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Embedded flash testing: overview and perspectives

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, we present a complete analysis of a particular failure mechanism, referred as disturb phenomenon. Moreover, we analyze the efficiency of a particular test sequence to detect this disturb phenomenon. Finally we conclude on the interest to develop new test infrastructure well adapted to the eFlash environment

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International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.

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