{"title":"同步器桥接缺陷故障建模与分析","authors":"Hyoung-Kook Kim, W. Jone","doi":"10.1109/NAECON.2008.4806580","DOIUrl":null,"url":null,"abstract":"This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"144 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fault Modeling and Analysis for Bridging Defects in a Synchronizer\",\"authors\":\"Hyoung-Kook Kim, W. Jone\",\"doi\":\"10.1109/NAECON.2008.4806580\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains.\",\"PeriodicalId\":254758,\"journal\":{\"name\":\"2008 IEEE National Aerospace and Electronics Conference\",\"volume\":\"144 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE National Aerospace and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.2008.4806580\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE National Aerospace and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.2008.4806580","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fault Modeling and Analysis for Bridging Defects in a Synchronizer
This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains.
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