用于三元码制的Delta-Sigma ADC(第一部分:调制器实现)

2007 International Symposium on Signals, Circuits and Systems Pub Date : 2007-07-13 DOI:10.1109/ISSCS.2007.4292653

A. Korotkov, D. Morozov, M. Pilipko, A. Sinha

{"title":"用于三元码制的Delta-Sigma ADC(第一部分:调制器实现)","authors":"A. Korotkov, D. Morozov, M. Pilipko, A. Sinha","doi":"10.1109/ISSCS.2007.4292653","DOIUrl":null,"url":null,"abstract":"The paper presents realization of the delta-sigma modulator of analog-to-digital converter (ADC) for ternary code signal processing. The modulator corresponds to the second order structure which was simulated on the circuit level. The evaluation demonstrates following characteristics of the modulator: frequency range is about 1 MHz, signal-to-noise ratio (SNR) is 60 dB, and power consumption is about 20 mW.","PeriodicalId":225101,"journal":{"name":"2007 International Symposium on Signals, Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Delta-Sigma ADC for Ternary Code System (Part I: Modulator Realization)\",\"authors\":\"A. Korotkov, D. Morozov, M. Pilipko, A. Sinha\",\"doi\":\"10.1109/ISSCS.2007.4292653\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents realization of the delta-sigma modulator of analog-to-digital converter (ADC) for ternary code signal processing. The modulator corresponds to the second order structure which was simulated on the circuit level. The evaluation demonstrates following characteristics of the modulator: frequency range is about 1 MHz, signal-to-noise ratio (SNR) is 60 dB, and power consumption is about 20 mW.\",\"PeriodicalId\":225101,\"journal\":{\"name\":\"2007 International Symposium on Signals, Circuits and Systems\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on Signals, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCS.2007.4292653\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on Signals, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2007.4292653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

本文介绍了用于三进制码信号处理的模数转换器(ADC)的δ - σ调制器的实现。该调制器对应于电路级模拟的二阶结构。该调制器具有以下特点:频率范围约为1 MHz，信噪比(SNR)为60 dB，功耗约为20 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Delta-Sigma ADC for Ternary Code System (Part I: Modulator Realization)

The paper presents realization of the delta-sigma modulator of analog-to-digital converter (ADC) for ternary code signal processing. The modulator corresponds to the second order structure which was simulated on the circuit level. The evaluation demonstrates following characteristics of the modulator: frequency range is about 1 MHz, signal-to-noise ratio (SNR) is 60 dB, and power consumption is about 20 mW.

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2007 International Symposium on Signals, Circuits and Systems

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