Combinatorial Effects of Bit and Byte Justification in SDH Networks

Existing Plesiochronous Digital Hierarchy networks synchronize signals by using fixed bit justification ratios. Justification bit opportunities are used a fixed percentage of the time in order to match the tributary to the transmission bit rate. Synchronous Digital Hierarchy Networks are different in that they use byte justifications instead of bit justifications. This important difference places new demands on SDH desynchronizers. These new demands are a result of the bit justification opportunities still present in lower order tributaries combining with the byte justification niechanisms provided in the SDH transmission. This paper examines the relative effects of bit justification in 2048 kbit/s signals in conjunction with the corresponding byte justification in SDH transmission networks to determine the dynamics of SDH network plesiochronous desynchronizer buffers. Additional effects which cause variations in desynchronizer buffers such as payload structures and pointer gaping effects are also examined.