基于统计的片上互连最坏情况建模快速生成

N. Chang, V. Kanevsky, O. S. Nakagawa, K. Rahmat, Soo-Young Oh
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引用次数: 20

摘要

在本文中,我们描述了一种新的方法,用于获得基于统计的最坏情况(即3-/spl sigma/) R(电阻),C(电容)和给定互连相关工艺参数变化的延迟。我们的方法是基于加权根和平方法来导出3-/spl sigma/ c。基于蒙特卡罗的方法用于生成3-/spl sigma/ R以及随机分布式RC网络,以获得长互连网络(如全局关键路径)的真实3-/spl sigma/延迟。使用该方法对0.35 /spl mu/m工艺进行长临界净分析,与传统的斜角最坏情况延迟相比,可以实现3-/spl σ /延迟估计提高70%以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fast generation of statistically-based worst-case modeling of on-chip interconnect
In this paper, we describe a novel methodology for obtaining statistically-based worst case (i.e. 3-/spl sigma/) R (resistance), C (capacitance), and delay given variations in interconnect-related process parameters. Our approach is based on a weighted root-sum square method to derive 3-/spl sigma/ C. A Monte Carlo-based method is used for the generation of 3-/spl sigma/ R as well as randomized distributed RC nets to obtain realistic 3-/spl sigma/ delays for long interconnect nets such as global critical paths. Using this methodology for a long critical net analysis on a 0.35 /spl mu/m process, a more than 70% improvement in 3-/spl sigma/ delay estimation compared with the traditional skew-corner worst case delay can be realized.
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