Efficient Hardware Acceleration of Chinese Remainder Theorem for Fully Homomorphic Encryption

Fully homomorphic encryption (FHE) has recently received huge attention because of its ability to perform operations on encrypted data. FHE requires arithmetic operations on data with Large Arithmetic Word Size (LAWS) over 64-bit. The Chinese Remainder Theorem (CRT) is used to process such operations in 64-bit architecture. However, since the CRT itself involves the operations on LAWS data, long latency and many hardware resources are required to process the operations. In this paper, we propose a hardware architecture that performs LAWS operation of CRT and inverse CRT (iCRT) through recursive arithmetic operation of Small Arithmetic Word Size (SAWS) data, reducing resource usage and accelerating execution. The proposed hardware was implemented to operate at 100 MHz frequency on the FPGA, and showed latency of 91.2 us and 24.39 us, respectively, for executing CRT and iCRT with only 68 DSP and 65 LUTRAM, and a small number of LUTs and FFs.