{"title":"考虑节点连通性的BIST输入分组方法","authors":"Byung-Gu Choi, Yoon-Seok Chang, Dong-Wook Kim","doi":"10.1109/APASIC.1999.824092","DOIUrl":null,"url":null,"abstract":"At present, BIST is a major test strategy with features of automatic test and possibility of at-speed test. But BIST has significant problems for hardware overhead and consumes impractical test time (test length); in the case of CUT it has a large number of primary inputs. We proposed a new method called input grouping which is helpful to reduce test length for BIST application. This method partitions inputs by considering nodal connectivity with respect to internal nodes. To achieve this purpose we proposed some definitions for test points, conditions for a node to be a test point, and a procedure to find test points in a given circuits. The test points were applied to form a BIST structure to reduce the test time. The experimental result showed that BIST TPGs based on this method achieves tremendous reduction in test time compared to the case using pseudorandom patterns for various example circuits.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Input grouping method considering nodal connectivity for BIST test time reduction\",\"authors\":\"Byung-Gu Choi, Yoon-Seok Chang, Dong-Wook Kim\",\"doi\":\"10.1109/APASIC.1999.824092\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"At present, BIST is a major test strategy with features of automatic test and possibility of at-speed test. But BIST has significant problems for hardware overhead and consumes impractical test time (test length); in the case of CUT it has a large number of primary inputs. We proposed a new method called input grouping which is helpful to reduce test length for BIST application. This method partitions inputs by considering nodal connectivity with respect to internal nodes. To achieve this purpose we proposed some definitions for test points, conditions for a node to be a test point, and a procedure to find test points in a given circuits. The test points were applied to form a BIST structure to reduce the test time. The experimental result showed that BIST TPGs based on this method achieves tremendous reduction in test time compared to the case using pseudorandom patterns for various example circuits.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824092\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824092","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Input grouping method considering nodal connectivity for BIST test time reduction
At present, BIST is a major test strategy with features of automatic test and possibility of at-speed test. But BIST has significant problems for hardware overhead and consumes impractical test time (test length); in the case of CUT it has a large number of primary inputs. We proposed a new method called input grouping which is helpful to reduce test length for BIST application. This method partitions inputs by considering nodal connectivity with respect to internal nodes. To achieve this purpose we proposed some definitions for test points, conditions for a node to be a test point, and a procedure to find test points in a given circuits. The test points were applied to form a BIST structure to reduce the test time. The experimental result showed that BIST TPGs based on this method achieves tremendous reduction in test time compared to the case using pseudorandom patterns for various example circuits.