Highly stable power efficient noise tolerant circuits for analog and digital systems

Noise is an important factor in the analog and digital circuits which determine the characteristics of the system. The work aims at developing a noise robust circuit with high frequency response and the same can be implemented in a dynamic logic system with reduced number of transistor and also the dynamic logic will have the probability of signal switching activity to be low which will subsequently reduce the power of the system. The circuits have been constructed using cadence ADE and the same has been simulated with Spectre using 45nm GPDK technology. The simulation results show that the power consumption has been reduced multi-fold and the bandwidth has been increased by 102 Hz and the delay is reduced by 50%.