轻量级卷积神经网络YOLO v3- Tiny算法在FPGA上的目标检测

Jitong Xin, Meiyi Cha, Luojia Shi, Chunyu Long, Hairong Li, Fangcong Wang, Peng Wang
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引用次数: 0

摘要

随着人工智能的快速发展,神经网络的卷积已经在多个行业得到部署,在国防安全、交通监控、医学研究等方面都有一定的应用。然而,由于速度和功耗的限制,卷积神经网络在边缘计算和移动设备等方面的实现仍然受到很大程度的限制。为此,我们设计了一个基于FPGA的轻量级卷积神经网络。本文采用YOLOv3- Tiny算法,该算法具有执行速度快、计算量小、体积小等特点,适合部署在FPGA等嵌入式设备上。本文采用16位定点量化、专用数据存储和用verilog -硬件描述语言编写的卷积计算硬件电路,消耗512个dsp,单帧图像识别耗时37.037 ms,功耗9.611W。该系统基本实现了目标检测的设计目标。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Lightweight convolutional neural network of YOLO v3- Tiny algorithm on FPGA for target detection
With the rapid development of artificial intelligence, the convolution of the neural network has been deploying across a range of industries, and has certain applications in national defense security, transportation monitoring and medical research. However, due to the constraints of speed and the power consumption, convolutional neural networks are still limited to a great extent in the implementation of the edge computing and mobile devices, etc. For this reason, we design a lightweight convolutional neural network based on FPGA. In this paper, we use the YOLOv3- Tiny algorithm, which is fast in execution, small in computation and small in size, is suitable for deployments on embedded devices such as FPGA. This paper uses 16-bit fixed-point quantization, special data storage and hardware circuit for convolutional computation written in verilog - hardware description language, consumes 512 DSPs, consumes 37.037 ms to recognize a single image frame, and consumes 9.611W. The system basically achieves the design goal of target detection.
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