用于植入式神经信号记录应用的电流偏置伪电阻

S. Yuan, L. G. Johnson, C.C. Liu, C. Hutchens, R. Rennaker
{"title":"用于植入式神经信号记录应用的电流偏置伪电阻","authors":"S. Yuan, L. G. Johnson, C.C. Liu, C. Hutchens, R. Rennaker","doi":"10.1109/MWSCAS.2008.4616885","DOIUrl":null,"url":null,"abstract":"A current biased pseudo-resistor for implantable extracellular neural signal recording applications is introduced in this work. The pseudo-resistor, which is biased in the subthreshold region, is able to realize a very large resistance while keeping the silicon area small. A wide range of resistances can also be implemented by changing the bias current. Issues concerning the linearity of the pseudo-resistor and the frequency response of the pseudo-resistor bias are discussed in this paper. The chips were fabricated in a 0.5 micron 3M2P CMOS process and the test results show that the current biasing method is able to realize more reliable resistance than the voltage biasing method.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"Current biased pseudo-resistor for implantable neural signal recording applications\",\"authors\":\"S. Yuan, L. G. Johnson, C.C. Liu, C. Hutchens, R. Rennaker\",\"doi\":\"10.1109/MWSCAS.2008.4616885\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A current biased pseudo-resistor for implantable extracellular neural signal recording applications is introduced in this work. The pseudo-resistor, which is biased in the subthreshold region, is able to realize a very large resistance while keeping the silicon area small. A wide range of resistances can also be implemented by changing the bias current. Issues concerning the linearity of the pseudo-resistor and the frequency response of the pseudo-resistor bias are discussed in this paper. The chips were fabricated in a 0.5 micron 3M2P CMOS process and the test results show that the current biasing method is able to realize more reliable resistance than the voltage biasing method.\",\"PeriodicalId\":118637,\"journal\":{\"name\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2008.4616885\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 51st Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2008.4616885","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19

摘要

本文介绍了一种用于植入式细胞外神经信号记录的电流偏置伪电阻器。伪电阻器偏置在亚阈值区域,可以在保持小硅面积的同时实现非常大的电阻。通过改变偏置电流,也可以实现大范围的电阻。本文讨论了伪电阻的线性度和伪电阻偏置的频率响应问题。在0.5微米3M2P CMOS工艺中制备了芯片,测试结果表明,电流偏置法比电压偏置法能够实现更可靠的电阻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Current biased pseudo-resistor for implantable neural signal recording applications
A current biased pseudo-resistor for implantable extracellular neural signal recording applications is introduced in this work. The pseudo-resistor, which is biased in the subthreshold region, is able to realize a very large resistance while keeping the silicon area small. A wide range of resistances can also be implemented by changing the bias current. Issues concerning the linearity of the pseudo-resistor and the frequency response of the pseudo-resistor bias are discussed in this paper. The chips were fabricated in a 0.5 micron 3M2P CMOS process and the test results show that the current biasing method is able to realize more reliable resistance than the voltage biasing method.
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